This invention generally relates to the field of communication systems and more particularly to a digital filter that is used for generating a direct sequence spread spectrum modulation signal.
Digital wireless communication systems that support voice and data services are becoming widely used throughout the world. For example, in the U.S., the Telecommunication Industry Association (TIA) has published an Interim Standard known as IS-95 that specifies a cellular spread spectrum communication system.
Spread spectrum communication systems are gaining acceptance among cellular system operators, mainly because they provide spectral efficiency and frequency planning simplicity by sharing the time and frequency domains for all users simultaneously. The cellular spread spectrum communication system specified by the IS-95 standard uses a code division multiple access (CDMA) method for communicating voice and data over wideband radio frequency (RF) channels. In Japan, a similar spread spectrum system is specified under the Japanese Standard JSTD-008. Another digital communication standard, which is specified by the European Telecommunication Standard Institute (ETSI), GSM is known as Global Standard for Mobile Communication (GSM). However, GSM uses a time division multiple access (TDMA) method, as opposed to the CDMA method, to communicate voice and data over relatively narrowband RF channels.
Typically, cellular spread spectrum systems use a so-called xe2x80x9cdirect sequencexe2x80x9d spread spectrum (DS-SS) modulation method that allows for simultaneous transmission of distinct information signals to separate users over a common wideband RF channel. According to one DS-SS modulation method, information signals having a specified bit rate are directly modulated by corresponding spreading codes or sequences to produce quadrature modulation signals for simultaneous transmission in accordance with a specified air interface. The spreading code for each information signal includes a sequence of xe2x80x9cchipsxe2x80x9d occurring at a specified chip rate. For example, IS-95 specifies a 1.2288 Mbits/second which is much higher than the bit rate of the information signal being transmitted. The simultaneously transmitted information signals are distinguished from each other by a unique spreading sequence known as Pseudo-random (PN) sequence. In order to recover a particular transmitted information signal from among other information signals transmitted simultaneously, a DS-CDMA receiver, for example, one at a user""s mobile station, multiplies the received signal by a locally generated unique user assigned PN sequence and integrates the result. In so doing, the user identifies the information signal intended for it, as distinct from the information signals intended for other users. Conventionally, the spreading sequence is sampled at a specified sampling rate and applied to a multi-tap digital FIR filter, which subjects each sample to a corresponding FIR weight coefficient, before generating a spread spectrum modulation signal.
In one related prior art, U.S. Pat. No. 5,530,722 to Dent describes an improved quadrature modulator using balanced RC filters. In one implementation, the balanced RC filters are driven by complementary and high-bit-rate sigma-delta representations of I and Q signals respectively, which are extracted from a look-up table in dependence on a succession of modulation symbols. In another implementation, where the number of successive symbols on which the sigma-delta representation depends would have resulted in a look-up table of excessive size, the disclosed filters use a number of coefficients, after which the filtered values are digitally converted to an over-sampled sigma-delta representation.
Also, U.S. Pat. No. 5,867,537 to Dent describes balanced transversal filters for generating filtered I and Q modulating waveforms that are dependent on a succession of modulation bits. Each one of the succession of bits are delayed in a register, and the delayed bit (or an inverted delayed bit) is applied to a resistive combining network according to a positive or a negative FIR weight coefficient that is associated with the delayed bit. This prior art also discloses a complementary resistor network that uses opposite bit polarities for producing balanced I and Q modulating waveforms.
In another related prior art disclosed in U.S. Pat. No. 4,644,561 to Paneth et al., (Paneth) a modem for modulating and demodulating multi-bit symbols on a radio frequency carrier uses multi-phase modulation, such as 16-phase modulation. The modulation signals are generated using a digital filter, the output of which comprises alternating In-phase (I) and Quadrature (Q) as well as xe2x88x92I, xe2x88x92Q signals. After D-to-A conversion, these alternating signals represent a modulated signal on an intermediate frequency that corresponds to xc2xc of the sampling rate used at the input of the digital filter.
The digital filter disclosed in Paneth employs a read-only-memory (ROM), which stores pre-computed and partially weighted sums of symbols derived over portions of a window of L successive modulation symbols. The partially weighted sums, which are outputted by the ROM, are D-to-A converted sequentially and allowed effectively to add in a subsequent bandpass filter to form a complete weighted sum. Also, U.S. Pat. No. 4,996,697 to Critchlow et al. describes blanking the output of the D-to-A convertor waveform generator system disclosed in Paneth in order to de-glitch the D-to-A output signal, thereby preventing impurities in the transmission spectrum. However, one of the drawbacks of this arrangement is the requirement for a large size ROM for storing pre-computed weighted sums of all symbols in the window.
The IS-95 standard specifies a 48-tap FIR filter for filtering I and Q signals, prior to quadrature modulation. FIG. 1 illustrates one such conventional 48-tap FIR filter 10, which operates at a sampling rate of four times the chip rate. As shown, the digital filter 10 receives input signal samples that are represented by 1, 0, and xe2x88x921 samples. The +1 and xe2x88x921  samples correspond to chip values of Boolean xe2x80x9c1xe2x80x9dand Boolean xe2x80x9c0xe2x80x9d respectively, and 0 samples corresponds to no value of significance for transmission. In the instant specification, the + or xe2x88x921 samples are collectively referred to as non-zero samples. The filter 10 includes 48 memory or delay elements 12, indicated by Zxe2x88x921, which are connected in a chain to receive the successive signal samples at four times the chip rate. This arrangement excites the filter 10 with a series of short, i.e., xc2xc chip period, impulses that are applied to corresponding FIR coefficients, C1 to C48, to provide the filter outputs. These coefficients are implemented using suitable weighting networks, for example, digital multipliers 14. The filter outputs are summed, via a summer 16, to generate digital output bytes or words at four times the chip rate.
Generally, the output words are converted to corresponding analog voltage levels using a D-to-A convertor 18. The output of the D-to-A converter 18 is applied to an anti-aliasing filter 20 that removes undesired components. As shown, the impulses are separated by a number of consecutive zero samples, where every fourth sample is a non-zero sample followed by three zero samples. Consequently, during each one of the four samples occurring during a chip period, only 12 taps contribute to the filter output.
In accordance with Paneth, the filter 10 is simplified as described later in detail through four 12-tap filters having input and outputs multiplexed and de-multiplexed at four times the chip rate, instead of using a 48-tap filter. Moreover, since a twelve-tap filter driven by binary input values produces 4096 different output values, four 4096-element storage devices, for example, ROMs or RAMs, may store corresponding tables of pre-computed weight values for all combination of twelve inputs, i.e., 4xc3x97212 values, thereby replacing the four 12-tap filters.
Also, the four 4096-element storage devices may be combined into a single 16384-element storage device that is addressable by twelve address lines carrying non-zero samples. Under this arrangement, the outputs of the 16384-element ROM may be selected in a de-multiplexed fashion using a clock rate that is four-times the chip rate. In order to further reduce the ROM size, the address lines may be split into two 6-bit lines, with each 6-bit line addressing a respective one of two 256-element (4xc3x9764) ROMs. The outputs of the two 256-element ROMs may then be added to obtain the filter outputs.
It is, however, desired to reduce the complexity of the digital filter even further. Among other things, one of the advantages of a less complex digital filter is reduced power consumption, specially when such filter is incorporated in mobile units that operate on limited battery power. Therefore, there exists a need for a simplified digital filter, particularly, a simplified FIR filter used for generating direct sequence spread spectrum modulation signals.
Briefly, according to one aspect of the present invention, a digital filter that generates spread-spectrum signals reduces complexity by taking advantage of time-reversal symmetry of the impulses derived at every predefined number of non-zero samples, thereby reducing the size of a storage device that stores pre-computed values in half The spread spectrum modulated signals are generated by receiving a number of input samples representing a digital signal as successive bits at a specified rate, wherein the modulation signals are generated at an output sample rate of more than one sample per symbol period. The successive bits are grouped into a first sub-group of bits and a second sub-group of bits that are alternately applied to a first set of address lines of a storage device. The storage device, which stores pre-computed values that correspond to input-sample filter responses, for example, FIR filter responses, is addressable by the combination of the first set of address lines and a second set of different address lines. The time-reversal symmetry according to this method of the invention is exploited by modifying the bit pattern applied to the second set of address lines, depending on whether the first sub-group of bits or the second sub-group of bits are applied to the first set of address lines. The bit pattern of the second set of address lines corresponds to the more than one sample per symbol period. According to one exemplary embodiment, a 256-element ROM or (RAM) is used with multiplexing at 8 times the chip rate to implement the filter of the invention. According to another embodiment, I and Q multiplexing is used at 16 times the chip rate to implement a quadrature digital filter using a single 256-element ROM (or RAM), which is accessed at 16 times the chip rate.
According to another aspect of the invention, means are provided for smoothly starting and terminating transmission of modulated signals by providing a ternary input signal. Transmission commences with a ternary input register initialized to contain zero value elements. Then, successive non-zero chip values are clocked in, while a filtered output is transmitted. In order to terminate transmission after the last non-zero chip value has been clocked in, the last chip is followed by clocking in a succession of zero values, while the filter output continues to be transmitted. When the ternary input register set contains only zero values in all its elements, the transmission may be terminated. The increase in the address space for the storage device that stores a look-up table when ternary digits are used is compensated in one of a variety of disclosed methods. A first method uses binary logic to reduce the address space by taking into account those combinations of digits that do not arise in the application. A second method comprises excising memory locations corresponding to addresses that do not arise in the application.